CY7C346B35JC
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CYPRESS
CY7C342B-30JC
Complex Erasable Programmable Logic Device, 128 Cell, 30ns, 68 Pin, Plastic.CPLD Family 2.5K Gates 128 Macro Cells 50MHz Commercial 0.8um (CMOS) 5V 68-Pin PLCC
In stock: 230
On our shelves in San Jose. We do not dropship.
Stock on our shelves
Date code and country of origin on every lot.
| Quantity | Date code | Country of origin |
|---|---|---|
| 230 | 0015 | United States |
| 230 | 1 lot on the shelf | |
Need a specific date code, or all of it from a single lot? Tell us on the quote and we will confirm before shipping.
Specifications
| Manufacturer | CYPRESS |
|---|---|
| Manufacturer part number | CY7C342B-30JC |
| Our part number | CY7C342B30JC |
| Category | IC |
| Description | Complex Erasable Programmable Logic Device, 128 Cell, 30ns, 68 Pin, Plastic.CPLD Family 2.5K Gates 128 Macro Cells 50MHz Commercial 0.8um (CMOS) 5V 68-Pin PLCC |
| Date codes in stock | 0015 |
Compliance & export
| ECCN | EAR99 |
|---|---|
| Country of origin | United States |
Classification is provided for reference and confirmed on the invoice. Certificate of conformance and date-code guarantee on request — ask with your order.
Description
CY7C342B-30JC CYPRESSThe CY7C342B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX® architecture is 100% user-configurable, allowing the device to accommodate a variety of independent logic functions.The speed and density of the CY7C342B allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C342B allows the replacement of over 50 TTL devices. By replacing large amounts of logic, the CY7C342B reduces board space, part count, and increases system reliabilityThe 128 macrocells in the CY7C342B are divided into eight LABs, 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip.HTS: 8542.39.00.01DOWNLOAD DATASHEET
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